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freescale semiconductor data sheet: technical data document number: mc9s08qe128 rev. 7, 10/2008 ? freescale semiconductor, inc., 2008. all rights reserved. freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. mc9s08qe128 ? 8-bit hcs08 central processor unit (cpu) ? up to 50.33-mhz hcs08 cpu above 2.4v, 40-mhz cpu above 2.1v, and 20-mhz cpu above 1.8v, across temperature range ? hc08 instruction set with added bgnd instruction ? support for up to 32 interrupt/reset sources ?on-chip memory ? flash read/program/erase over full operating voltage and temperature ? random-access memory (ram) ? security circuitry to prev ent unauthorized access to ram and flash contents ? power-saving modes ? two low power stop modes; reduced power wait mode ? peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode ? very low power external oscillator can be used in stop3 mode to provide accurate clock to active peripherals ? very low power real time counter for use in run, wait, and stop modes with internal and external clock sources ?6 s typical wake up time from stop modes ? clock source options ? oscillator (xosc) ? loop- control pierce oscillator; crystal or ceramic resonator range of 31.25 khz to 38.4 khz or 1 mhz to 16 mhz ? internal clock source (ics) ? fll controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation; supports cpu freq. from 2 to 50.33 mhz ? system protection ? watchdog computer operating properly (cop) reset with option to run from dedicated 1-khz internal clock source or bus clock ? low-voltage detection with reset or interrupt; selectable trip points ? illegal opcode detection with reset ? flash block protection ? development support ? single-wire background debug interface ? breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints) ? on-chip in-circuit emulator (ice) debug module containing two comparators and nine trigger modes. eight deep fifo for storing change-of-flow addresses and event-only data. debug module supports both tag and force breakpoints. ? adc ? 24-channel, 12-bit resolution; 2.5 s conversion time; automatic comp are function; 1.7 mv/ c temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6v to 1.8v ? acmpx ? two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to tpm module; operation in stop3 ? scix ? two scis with full duplex non-return to zero (nrz); lin master extended break generation; lin slave extended break detection; wake up on active edge ? spix? two serial peripheral interfaces with full-duplex or single-wire bidirectional; double-buffered transmit and receive; msb-first or lsb-first shifting ? iicx ? two iics with; up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing ? tpmx ? one 6-channel and two 3-channel; selectable input capture, output compar e, or buffered edge- or center-aligned pwms on each channel ? rtc ? 8-bit modulus counter with binary or decimal based prescaler; external cl ock source for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 khz) for cyclic wake-up without external components ? input/output ? 70 gpios and 1 input-only and 1 output-only pin ? 16 kbi interrupts with selectable polarity ? hysteresis and configurable pull-up device on all input pins; configurable slew rate and drive strength on all output pins. ? set/clr registers on 16 pins (ptc and pte) 80-lqfp case 917a 14 mm 2 64-lqfp case 840f 10 mm 2 48-qfn case 1314 7 mm 2 32-lqfp case 873a 7 mm 2 44-lqfp case 824d 10 mm 2 mc9s08qe128 series covers: mc9s08qe128, mc9s08qe96, mc9s08qe64 an energy efficient solution by freescale
mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 2 table of contents 1 mc9s08qe128 series comparison. . . . . . . . . . . . . . . . . . . . .4 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . .12 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . .12 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .13 3.5 esd protection and latch-up immunity . . . . . . . . . . . .14 3.6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7 supply current characteristics . . . . . . . . . . . . . . . . . . .18 3.8 external oscillator (xosc) characteristics . . . . . . . . .21 3.9 internal clock source (ics) characteristics . . . . . . . . .22 3.10 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.10.1 control timing . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.2 tpm module timing . . . . . . . . . . . . . . . . . . . . . 26 3.10.3 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.11 analog comparator (acmp) electricals . . . . . . . . . . . 30 3.12 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.13 flash specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 device numbering system . . . . . . . . . . . . . . . . . . . . . 34 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 mechanical drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 35 6 product documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 3 figure 1. mc9s08qe128 series block diagram tpm2ch2-0 tpm1ch2-0 analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic1) serial peripheral interface module (spi1) user flash user ram 128k / 96k / 64k hcs08 core cpu bdc 6-channel timer/pwm module (tpm3) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) reset v refl v refh 8k / 6k / 4k bkgd/ms interface (sci1) serial communications miso1 ss1 spsck1 3-channel timer/pwm module (tpm2) real time counter (rtc) debug module (dbg) irq pta3/kbi1p3/scl1/adp3 pta4/acmp1o/bkgd/ms pta5/irq/tpm1clk/reset pta2/kbi1p2/sda1/adp2 pta1/kbi1p1/tpm2ch0/adp1/acmp1- pta0/kbi1p0/tpm1ch0/adp0/acmp1+ port a pta6/tpm1ch2/adp8 pta7/tpm2ch2/adp9 mosi1 ptb3/kbi1p7/mosi1/adp7 ptb4/tpm2ch1/miso1 ptb5/tpm1ch1/ss1 ptb2/kbi1p6/spsck1/adp6 ptb1/kbi1p5/txd1/adp5 ptb0/kbi1p4/rxd1/adp4 port b ptb6/sda1/xtal ptb7/scl1/extal ptc3/tpm3ch3 ptc4/tpm3ch4/rsto ptc5/tpm3ch5/acmp2o ptc2/tpm3ch2 ptc1/tpm3ch1 ptc0/tpm3ch0 port c ptc6/rxd2/acmp2+ ptc7/txd2/acmp2- ptd3/kbi2p3/ss2 ptd4/kbi2p4 ptd5/kbi2p5 ptd2/kbi2p2/miso2 ptd1/kbi2p1/mosi2 ptd0/kbi2p0/spsck2 port d ptd6/kbi2p6 ptd7/kbi2p7 pte3/ss1 pte4 pte5 pte2/miso1 pte1/mosi1 tpm2clk port e pte6 pte0/tpm2clk/spsck1 ptf3/adp13 ptf4/adp14 ptf5/adp15 ptf2/adp12 ptf1/adp11 ptf0/adp10 port f ptf6/adp16 ptf7/adp17 ptg1 ptg2/adp18 ptg3/adp19 port g ptg4/adp20 ptg5/adp21 ptg0 v ss v dd v ssa v dda bkp int analog comparator (acmp2) interface (sci2) serial communications 6 tpm3ch5-0 - v refh /v refl internally connected to v dda /v ssa in 48-pin and 32-pin packages - v dd and v ss pins are each internally connecte d to two pads in 32-pin package ptg6/adp22 ptg7/adp23 source (ics) internal clock port j port h ptj1 ptj2 ptj3 ptj4 ptj5 ptj0 ptj6 ptj7 pth1 pth2 pth3 pth4 pth5 pth0 pth6/scl2 pth7/sda2 iic module (iic2) analog-to-digital converter (adc) 24-channel,12-bit 3-channel timer/pwm module (tpm1) sda2 scl2 serial peripheral interface module (spi2) miso2 ss2 spsck2 mosi2 extal xtal 10 sda1 scl1 acmp2- acmp2+ acmp2o rxd1 txd1 rxd2 txd2 tpm3clk 3 tpm1clk pte7/tpm3clk
mc9s08qe128 series data sheet, rev. 7 mc9s08qe128 series comparison freescale semiconductor 4 1 mc9s08qe128 series comparison the following table compares the various device de rivatives available within the mc9s08qe128 series. table 1. mc9s08qe128 series features by mcu and package feature mc9s08qe128 mc9s08qe96 mc9s08qe64 flash size (bytes) 131072 98304 65536 ram size (bytes) 8064 6016 4096 pin quantity 806448448064484464484432 acmp1 yes acmp2 yes adc channels 24 22 10 10 24 22 10 10 22 10 10 10 dbg yes ics yes iic1 yes iic2 yes yes no no yes yes no no yes no no no irq yes kbi 161616161616161616161612 port i/o 1 1 port i/o count does not include the i nput only pta5/irq/tpm1clk/reset or the output only pta4/acmp1o/bkgd/ms. 70 54 38 34 70 54 38 34 54 38 34 26 rtc yes sci1 yes sci2 yes spi1 yes spi2 yes tpm1 channels 3 tpm2 channels 3 tpm3 channels 6 xosc yes
pin assignments mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 5 2 pin assignments this section describes the pin assign ments for the available packages. see table 2 for pin availability by package pin-count. figure 2. pin assignments in 80-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 v refh v ssad v dd v refl v ddad v ss ptb7/scl1/extal pth7/sda2 ptd0/kbi2p0/spsck2 ptd1/kbi2p1/mosi2 pte6 ptb6/sda1/xtal pth6/scl2 pte7/tpm3clk pth1 pth0 pth3 pth2 pth5 pth4 ptc2/tpm3ch2 ptb4/tpm2ch1/miso1 ptb5/tpm1ch1/ss1 ptc3/tpm3ch3 ptd7/kbi2p7 ptc0/tpm3ch0 ptc1/tpm3ch1 ptd6/kbi2p6 ptd5/kbi2p5 ptb3/kbi1p7/mosi1/adp7 ptb2/kbi1p6/spsck1/adp6 pte5 ptf7/adp17 ptf6/adp16 ptf5/adp15 ptf4/adp14 ptd4/kbi2p4 v dd v ss pta7/tpm2ch2/adp9 ptb1/kbi1p5/txd1/adp5 ptb0/kbi1p4/rxd1/adp4 pta2/kbi1p2/sda1/adp2 pta3/kbi1p3/scl1/adp3 pta6/tpm1ch2/adp8 ptd3/kbi2p3/ss2 ptd2/kbi2p2/miso2 pte4 ptf0/adp10 ptf1/adp11 ptf2/adp12 ptf3/adp13 pte2/miso1 pta5/irq/tpm1clk/reset pta4/acmp1o/bkgd/ms pta0/kbi1p0/tpm1ch0/adp0/acmp1+ ptc7/txd2/acmp2- ptc5/tpm3ch5/acmp2o ptc4/tpm3ch4/rsto ptc6/rxd2/acmp2+ pte0/tpm2clk/spsck1 pte1/mosi1 pte3/ss1 ptg3/adp19 ptg2/adp18 ptg1 ptg0 ptg7/adp23 ptg6/adp22 ptg5/adp21 ptg4/adp20 ptj4 ptj5 ptj6 ptj7 ptj1 ptj0 ptj3 ptj2 pta1/kbi1p1/tpm2ch0/adp1/acmp1- pins in bold are added from the next smaller package.
mc9s08qe128 series data sheet, rev. 7 pin assignments freescale semiconductor 6 figure 3. pin assignments in 64-pin lqfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 v refh v ssad v dd v refl v ddad v ss ptb7/scl1/extal pth7/sda2 ptd0/kbi2p0/spsck2 ptd1/kbi2p1/mosi2 pte6 ptb6/sda1/xtal ptc2/tpm3ch2 ptb4/tpm2ch1/miso1 ptb5/tpm1ch1/ss1 ptc3/tpm3ch3 ptd7/kbi2p7 ptc0/tpm3ch0 ptc1/tpm3ch1 ptd6/kbi2p6 ptd5/kbi2p5 ptb3/kbi1p7/mosi1/adp7 ptb2/kbi1p6/spsck1/adp6 pte5 ptd4/kbi2p4 v dd v ss pta7/tpm2ch2/adp9 ptb1/kbi1p5/txd1/adp5 ptb0/kbi1p4/rxd1/adp4 pta2/kbi1p2/sda11/adp2 pta3/kbi1p3/scl1/adp3 pta6/tpm1ch2/adp8 ptd3/kbi2p3/ss2 ptd2/kbi2p2/miso2 pte4 pte2/miso1 pta5/irq/tpm1clk/reset pta4/acmp1o/bkgd/ms pta0/kbi1p0/tpm1ch0/adp0/acmp1+ pta1/kbi1p1/tpm2ch0/adp1/acmp1- ptc7/txd2/acmp2- ptc5/tpm3ch5/acmp2o ptc4/tpm3ch4/rsto ptc 6/rxd2/acmp2+ pte0/tpm2clk/spsck1 pte1/mosi1 pte3/ss1 ptf0/adp10 ptf1/adp11 ptf7/adp17 ptf6/adp16 ptf5/adp15 ptf4/adp14 ptf2/adp12 ptf3/adp13 ptg3/adp19 ptg2/adp18 ptg1 ptg0 pth6/scl2 pte7/tpm3clk pth1 pth0 pins in bold are added from the next smaller package.
pin assignments mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 7 figure 4. pin assignments in 48-pin qfn package 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 36 33 32 31 30 29 28 27 26 13 24 23 25 35 34 37 38 12 v refh v ssad v dd v refl v ddad v ss ptb7/scl1/extal ptb6/sda11/xtal pte7/tpm3clk ptd0/kbi2p0/spsck2 ptd1/kbi2p1/mosi2 pte6 ptc2/tpm3ch2 ptb4/tpm2ch1/miso1 ptb5/tpm1ch1/ss1 ptc3/tpm3ch3 ptd7/kbi2p7 ptc0/tpm3ch0 ptc1/tpm3ch1 ptd6/kbi2p6 ptd5/kbi2p5 ptb3/kbi1p7/mosi1/adp7 ptb2/kbi1p6/spsck1/adp6 pte5 ptd4/kbi2p4 v dd v ss pta7/tpm2ch2/adp9 ptb1/kbi1p5/txd1/adp5 ptb0/kbi1p4/rxd1/adp4 pta2/kbi1p2/sda1/adp2 pta3/kbi1p3/scl1/adp3 pta6/tpm1ch2/adp8 ptd3/kbi2p3/ss2 ptd2/kbi2p2/miso2 pte4 pte2/ miso1 pta5/irq/tpm1clk/reset pta4/acmp1o/bkgd/ms pta0/kbi1p0/tpm1ch0/adp0/acmp1+ pta1/kbi1p1/tpm2ch0/ad ptc7/txd2/acmp2- ptc5/tpm3ch5/acmp2o ptc4/tpm3ch4/rsto ptc6/rxd2/acmp2+ pte0/tpm2clk/ spsck1 pte1/ mosi1 pte3/ss1 pta1/kbi1p1/tpm2ch0/adp1/acmp1-
mc9s08qe128 series data sheet, rev. 7 pin assignments freescale semiconductor 8 figure 5. pin assignments in 44-pin lqfp package 44 34 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 33 32 31 30 29 28 27 26 25 24 12 22 23 v refh v ssad v dd v refl v ddad pte2 ptd4/kbi2p4 v ss ptc2/tpm3ch2 ptb4/tpm2ch1/miso1 ptb7/scl1/extal ptb6/sda1/xtal ptb5/tpm1ch1/ss1 ptc3/tpm3ch3 pta5/irq/tpm1clk/reset pta4/acmp1o/bkgd/ms ptd7/kbi2p7 ptc0/tpm3ch0 ptc1/tpm3ch1 v dd v ss ptd6/kbi2p6 ptd5/kbi2p5 pta0/kbi1p0/tpm1ch0/adp0/acmp1+ pta1/kbi1p1/tpm2ch0/adp1/acmp1- ptc7/txd2/acmp2- ptc5/tpm3ch5/acmp2o ptc4/tpm3ch4/rsto ptc6/rxd2/acmp2+ pta7/tpm2ch2/adp9 ptb3/kbi1p7/mosi1/adp7 ptb2/kbi1p6/spsck1/adp6 ptb1/kbi1p5/txd1/adp5 ptb0/kbi1p4/rxd1/adp4 pta2/kbi1p2/sda1/adp2 pta3/kbi1p3/scl1/adp3 pta6/tpm1ch2/adp8 pte0/tpm2clk pte1 pte7/tpm3clk ptd0/kbi2p0/spsck2 ptd1/kbi2p1/mosi2 ptd3/kbi2p3/ss2 ptd2/kbi2p2/miso2
pin assignments mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 9 figure 6. pin assignments 32-pin lqfp package ptd3/kbi2p3/ss2 v refh /v ddad 1 2 3 4 5 6 7 8 v refl /v ssad v ss 19 18 17 10 11 12 13 14 15 9 24 32 16 25 26 27 v dd 20 21 22 23 31 30 29 28 pta5/irq/tpm1clk/reset pta4/acmp1o/bkgd/ms pta7/tpm2ch2/adp9 pta0/kbip0/tpm1ch0/adp0/acmp1 ptc0/tpm3ch0 ptb3/kbi1p7/mosi1/adp7 ptb2/kbi1p6/spsck1/adp6 ptb1/kbi1p5/txd1/adp5 ptb0/kbi1p4/rxd1/adp4 pta2/kbip2/sda1/adp2 pta3/kbip3/scl1/adp3 pta1/kbip1/tpm2ch0/adp1/acmp1 ptc1/tpm3ch1 ptc2/tpm3ch2 ptb4/tpm2ch1/miso1 ptc7/txd2/acmp2- ptb6/sda1/xtal ptb5/tpm1ch1/ss1 ptc5/tpm3ch5/acmp2o ptc4/tpm3ch4/rsto ptc3/tpm3ch3 ptd0/kbi2p0/spsck2 ptd1/kbi2p1/mosi2 ptb7/scl1/extal ptd2/kbi2p2/miso2 pta6/tpm1ch2/adp8 ptc6/rxd2/acmp2+
mc9s08qe128 series data sheet, rev. 7 pin assignments freescale semiconductor 10 table 2. mc9s08qe128 series pin assignment by package and pin count pin number lowest m priority o highest 80 64 48 44 32 port pin alt 1 alt 2 alt 3 alt 4 1 1 1 1 1 ptd1 kbi2p1 mosi2 2 2 2 2 2 ptd0 kbi2p0 spsck2 3 3 ? ? ? pth7 sda2 4 4 ???pth6 scl2 5 ????pth5 6 ????pth4 7533?pte7 tpm3clk 86443 v dd 97554 v dda 10 8 6 6 ? v refh 11 9 7 7 ? v refl 12 10 8 8 5 v ssa 13 11 9 9 6 v ss 14 12 10 10 7 ptb7 scl1 extal 15 13 11 11 8 ptb6 sda1 xtal 16????pth3 17????pth2 18 14 ? ? ? pth1 19 15 ? ? ? pth0 20 16 12 ? ? pte6 21 17 13 ? ? pte5 22 18 14 12 9 ptb5 tpm1ch1 ss1 23 19 15 13 10 ptb4 tpm2ch1 miso1 24 20 16 14 11 ptc3 tpm3ch3 25 21 17 15 12 ptc2 tpm3ch2 26 22 18 16 ? ptd7 kbi2p7 27 23 19 17 ? ptd6 kbi2p6 28 24 20 18 ? ptd5 kbi2p5 29????ptj7 30????ptj6 31????ptj5 32????ptj4 33 25 21 19 13 ptc1 tpm3ch1 34 26 22 20 14 ptc0 tpm3ch0 35 27 ? ? ? ptf7 adp17 36 28 ? ? ? ptf6 adp16 37 29 ? ? ? ptf5 adp15 38 30 ? ? ? ptf4 adp14 39 31 23 21 15 ptb3 kbi1p7 mosi1 adp7 40 32 24 22 16 ptb2 kbi1p6 spsck1 adp6
pin assignments mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 11 41 33 25 23 17 ptb1 kbi1p5 txd1 adp5 42 34 26 24 18 ptb0 kbi1p4 rxd1 adp4 43????ptj3 44????ptj2 45 35 ? ? ? ptf3 adp13 46 36 ? ? ? ptf2 adp12 47 37 27 25 19 pta7 tpm2ch2 adp9 48 38 28 26 20 pta6 tpm1ch2 adp8 49 39 29 ? ? pte4 50 40 30 27 ? v dd 51 41 31 28 ? v ss 52 42 ? ? ? ptf1 adp11 53 43 ? ? ? ptf0 adp10 54????ptj1 55????ptj0 56 44 32 29 ? ptd4 kbi2p4 57 45 33 30 21 ptd3 kbi2p3 ss2 58 46 34 31 22 ptd2 kbi2p2 miso2 59 47 35 32 23 pta3 kbi1p3 scl1 adp3 60 48 36 33 24 pta2 kbi1p2 sda1 adp2 61 49 37 34 25 pta1 kbi1p1 tpm2ch0 adp1 acmp1- 62 50 38 35 26 pta0 kbi1p0 tpm1ch0 adp0 acmp1+ 63 51 39 36 27 ptc7 txd2 acmp2- 64 52 40 37 28 ptc6 rxd2 acmp2+ 65????ptg7 adp23 66????ptg6 adp22 67????ptg5 adp21 68????ptg4 adp20 69 53 41 ? ? pte3 ss1 70 54 42 38 ? pte2 miso1 71 55 ? ? ? ptg3 adp19 72 56 ? ? ? ptg2 adp18 73 57 ? ? ? ptg1 74 58 ? ? ? ptg0 75 59 43 39 ? pte1 mosi1 76 60 44 40 ? pte0 tpm2clk spsck1 77 61 45 41 29 ptc5 tpm3ch5 acmp2o 78 62 46 42 30 ptc4 tpm3ch4 rsto 79 63 47 43 31 pta5 irq tpm1clk reset 80 64 48 44 32 pta4 acmp1o bkgd ms table 2. mc9s08qe128 series pin assignment by package and pin count (continued) pin number lowest m priority o highest 80 64 48 44 32 port pin alt 1 alt 2 alt 3 alt 4
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 12 3 electrical characteristics 3.1 introduction this section contains electrical and timing specifications for the mc9s08qe128 series of microcontrollers available at the time of publication. 3.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following cla ssification is used and the parameters are tagge d accordingly in the tables where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 3.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in table 4 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advise d that normal precautions be taken to av oid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs ar e tied to an appropriate logic voltage level (f or instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. table 3. parameter classifications p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characteri zation by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations. table 4. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to +3.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . i d r 25 ma storage temperature range t stg ?55 to 150 q c
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 13 3.4 thermal characteristics this section provides information about ope rating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being c ontrolled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current fo r each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in q c can be obtained from: t j = t a + (p d u t ja ) eqn. 1 where: t a = ambient temperature, q c t ja = package thermal resist ance, junction-to-ambient, q c/w p d = p int p i/o p int = i dd u v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mc u is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). table 5. thermal characteristics rating symbol value unit operating temperature range (packaged) t a ?40 to 85 q c maximum junction temperature t jm 95 q c thermal resistance single-layer board 32-pin lqfp t ja 82 q c/w 44-pin lqfp 68 48-pin qfn 81 64-pin lqfp t ja 69 q c/w 80-pin lqfp 60 thermal resistance four-layer board 32-pin lqfp t ja 54 q c/w 44-pin lqfp 46 48-pin qfn 26 64-pin lqfp t ja 50 q c/w 80-pin lqfp 47
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 14 for most applications, p i/o p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k y (t j + 273 q c) eqn. 2 solving equation 1 and equation 2 for k gives: k = p d u (t a + 273 q c) + t ja u (p d ) 2 eqn. 3 where k is a constant pertaining to the particular pa rt. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 3.5 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much less common on these devices th an on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. qual ification tests are pe rformed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test qu alification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd puls es the device no longer meets the device specification. complete dc parametric and functional testing is pe rformed per the applicable device specificat ion at room temperature followed by hot temperature, unless specified othe rwise in the device specification. table 6. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 : storage capacitance c 100 pf number of pulses per pin ? 3 machine series resistance r1 0 : storage capacitance c 200 pf number of pulses per pin ? 3 latch-up minimum input voltage limit ? 2.5 v maximum input voltage limit 7.5 v table 7. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm r 2000 ? v 2 machine model (mm) v mm r 200 ? v 3 charge device model (cdm) v cdm r 500 ? v 4 latch-up current at t a = 85 q ci lat r 100 ? ma
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 15 3.6 dc characteristics this section includes informatio n about power supply requiremen ts and i/o pin characteristics. table 8. dc characteristics num c characteristic symbol condition min typ 1 max unit 1 operating voltage 1.8 2 3.6 v 2 c output high voltage all i/o pins, low-drive strength v oh 1.8 v, i load = ?2 ma v dd ? 0.5 ? ? v p all i/o pins, high-drive strength 2.7 v, i load = ?10 ma v dd ? 0.5 ? ? t 2.3 v, i load = ?6 ma v dd ? 0.5 ? ? c1.8v, i load = ?3 ma v dd ? 0.5 ? ? 3d output high current max total i oh for all ports i oht ??100ma 4 c output low voltage all i/o pins, low-drive strength v ol 1.8 v, i load = 2 ma ? ? 0.5 v p all i/o pins, high-drive strength 2.7 v, i load = 10 ma ? ? 0.5 t 2.3 v, i load = 6 ma ? ? 0.5 c 1.8 v, i load = 3 ma ? ? 0.5 d output low current max total i ol for all ports i olt ??100ma 5 6 p input high voltage all digital inputs v ih v dd ! 2.7 v 0.70 x v dd ?? v cv dd ! 1.8 v 0.85 x v dd ?? 7 p input low voltage all digital inputs v il v dd ! 2.7 v ? ? 0.35 x v dd cv dd ! 1.8 v ? ? 0.30 x v dd 8 c input hysteresis all digital inputs v hys 0.06 x v dd ??mv 9p input leakage current all input only pins (per pin) |i in| v in = v dd or v ss ?? 1 p a 10 p hi-z (off-state) leakage current all input/output (per pin) |i oz| v in = v dd or v ss ?? 1 p a 11 p pull-up resistors all digital inputs, when enabled r pu 17.5 ? 52.5 k : 12 d dc injection current 3, 4, 5 single pin limit i ic v in < v ss , v in > v dd ?0.2 ? 0.2 ma total mcu limit, includes sum of all stressed pins ?5 ? 5 ma 13 c input capacitance, all pins c in ?? 8pf 14 c ram retention voltage v ram ?0.61.0v 15 c por re-arm voltage 6 v por 0.9 1.4 1.79 v 16 d por re-arm time t por 10 ? ? p s 17 p low-voltage detection threshold ? high range 7 v lvdh 8 v dd falling v dd rising 2.11 2.16 2.16 2.21 2.22 2.27 v
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 16 figure 7. pull-up and pull-down typical resistor values 18 p low-voltage detection threshold ? low range 7 v lvdl v dd falling v dd rising 1.80 1.86 1.82 1.90 1.91 1.99 v 19 p low-voltage warning threshold ? high range 7 v lvwh v dd falling v dd rising 2.36 2.36 2.46 2.46 2.56 2.56 v 20 p low-voltage warning threshold ? low range 7 v lvwl v dd falling v dd rising 2.11 2.16 2.16 2.21 2.22 2.27 v 21 c low-voltage inhibit reset/recover hysteresis 7 v hys ?50?mv 22 p bandgap voltage reference 9 v bg 1.15 1.17 1.18 v 1 typical values are measured at 25 q c. characterized, not tested 2 as the supply voltage rises, the lvd circuit will hold the mcu in reset until the supply has risen above v lvdl . 3 all functional non-supply pins are internally clamped to v ss and v dd . 4 input must be current limited to the value specified. to determine the value of the required current-limit ing resistor, calcula te resistance values for positive and negative clamp voltages, then use the lar ger of the two values. 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current great er than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples ar e: if no system clo ck is present, or if clock rate is very low (which would reduce overall power consumption). 6 maximum is highest voltage that por is guaranteed. 7 low voltage detection and warning limi ts measured at 1 mhz bus frequency. 8 run at 1 mhz bus frequency 9 factory trimmed at v dd = 3.0 v, temp = 25 q c table 8. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit pull-up resistor typicals v dd (v) pull-up resistor (k : ) 20 25 30 35 40 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 25 q c 85 q c ?40 q c pull-down resistor typicals v dd (v) pull-down resistance (k : ) 20 25 30 35 40 1.8 2.3 2.8 3.3 25 q c 85 q c ?40 q c 3.6
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 17 figure 8. typical low-side driv er (sink) characteristics ? low drive (ptxdsn = 0) figure 9. typical low-side driver (sink) characteristics ? high drive (ptxdsn = 1) figure 10. typical high-side (source) characteristics ? low drive (ptxdsn = 0) typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 typical v ol vs v dd v dd (v) v ol (v) 0 0.05 0.1 0.15 0.2 1234 25 q c 85 q c ?40 q c 25 q c, i ol = 2 ma 85 q c, i ol = 2 ma ?40 q c, i ol = 2 ma typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 0102030 typical v ol vs v dd v dd (v) v ol (v) 0 0.1 0.2 0.3 0.4 1234 i ol = 6 ma i ol = 3 ma i ol = 10 ma 25 q c 85 q c ?40 q c 25 q c 85 q c ?40 q c typical v dd ? v oh vs i oh at v dd = 3.0 v i oh (ma)) 0 0.2 0.4 0.6 0.8 1 1.2 ?20 ?15 ?10 ?5 0 typical v dd ? v oh vs v dd at spec i oh v dd (v) v dd ? v oh (v) 0 0.05 0.1 0.15 0.2 0.25 1234 v dd ? v oh (v) 25 q c 85 q c ?40 q c 25 q c, i oh = 2 ma 85 q c, i oh = 2 ma ?40 q c, i oh = 2 ma
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 18 figure 11. typical high-side (source) characteristics ? high drive (ptxdsn = 1) 3.7 supply current characteristics this section includes information about power supply current in various operating modes. table 9. supply current characteristics num c parameter symbol bus freq v dd (v) typ 1 max unit temp ( q c) 1 p run supply current fei mode, all modules on ri dd 25.165 mhz 3 16 18 ma ?40 to 25 p 16 20 85 t 20 mhz 14.4 ? ?40 to 85 t8 mhz6.5? t1 mhz1.4? 2 c run supply current fei mode, all modules off ri dd 25.165 mhz 3 11.5 12.3 ma ?40 to 85 t20 mhz9.5? t8 mhz4.6? t1 mhz1.0? 3 t run supply current lps=0, all modules off ri dd 16 khz fbilp 3 152 ? p a?40 to 85 t 16 khz fbelp 115 ? 4 t run supply current lps=1, all modules off, running from flash ri dd 16 khz fbelp 3 21.9 ? p a 0 to 70 ? ?40 to 85 t run supply current lps=1, all modules off, running from ram 7.3 ? 0 to 70 ? ?40 to 85 5 c wait mode supply current fei mode, all modules off wi dd 25.165 mhz 3 5.74 6 ma ?-40 to 85 t20 mhz4.57? t8 mhz2? t 1 mhz 0.73 ? typical v dd ? v oh vs i oh at v dd = 3.0 v i oh (ma) 0 0.2 0.4 0.6 0.8 ?30 ?25 ?20 ?15 ?10 ?5 0 typical v dd ? v oh vs v dd at spec i oh v dd (v) v dd ? v oh (v) 0 0.1 0.2 0.3 0.4 1234 i oh = ?10 ma i oh = ?6 ma i oh = ?3 ma v dd ? v oh (v) 25 q c 85 q c ?40 q c 25 q c 85 q c ?40 q c
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 19 6 p stop2 mode supply current s2i dd n/a 3 0.35 0.6 p a -40 to 25 c 0.98 2.0 70 p 2.5 7.5 85 c 2 0.25 0.5 -40 to 25 c 1.4 1.9 70 c 1.91 6.5 85 7 p stop3 mode supply current no clocks active s3i dd n/a 3 0.45 1.0 p a -40 to 25 c 1.99 4.2 70 p 5.0 15.0 85 c 2 0.35 0.7 -40 to 25 c 2.9 3.9 70 c 3.77 13.2 85 1 data in typical column was characterized at 3.0 v, 25c or is typical recommended value. table 10. stop mode adders num c parameter condition temperature (c) units -40 25 70 85 1 t lpo 50 75 100 150 na 2 t errefsten range = hgo = 0 1000 1000 1100 1500 na 3 t irefsten 1 1 not available in stop2 mode. 63 70 77 81 ua 4 t rtc does not include clock source current 50 75 100 150 na 5tlvd 1 lvdse = 1 90 100 110 115 ua 6tacmp 1 not using the bandgap (bgbe = 0) 18 20 22 23 ua 7tadc 1 adlpc = adlsmp = 1 not using the bandgap (bgbe = 0) 95 106 114 120 ua table 9. supply current characteristics (continued) num c parameter symbol bus freq v dd (v) typ 1 max unit temp ( q c)
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 20 figure 12. typical run i dd for fbe and fei, i dd vs. v dd (adc off, all other modules enabled) 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 1.8 2 2.2 2.4 2.6 2.8 3 vdd (v) idd (ma) fei: 24 mhz fbelp: 24 mhz fei: 8 mhz fbelp: 8 mhz fei: 1 mhz fbelp: 1 mhz
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 21 3.8 external oscillator (xosc) characteristics reference figure 13 and figure 14 for crystal or resonator circuits. table 11. xosc and ics specifications (temperature range = ?40 to 85 q c ambient) num c characteristic symbol min typ 1 1 data in typical column was characterized at 3.0 v, 25 q c or is typical recommended value. max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) high range (range = 1), high gain (hgo = 1) high range (range = 1), low power (hgo = 0) f lo f hi f hi 32 1 1 ? ? ? 38.4 16 8 khz mhz mhz 2d load capacitors low range (range=0), low power (hgo=0) other oscillator settings c 1, c 2 see note 2 see note 3 2 load capacitors (c 1 ,c 2 ), feedback resistor (r f ) and series resistor (r s ) are incorporated inte rnally when range=hgo=0. 3 see crystal or resonator manufacturer?s recommendation. 3d feedback resistor low range, low power (range=0, hgo=0) 2 low range, high gain (range=0, hgo=1) high range (range=1, hgo=x) r f ? ? ? ? 10 1 ? ? ? m : 4d series resistor ? low range, low power (range = 0, hgo = 0) 2 low range, high gain (range = 0, hgo = 1) high range, low power (range = 1, hgo = 0) high range, high gain (range = 1, hgo = 1) t 8 mhz 4 mhz 1 mhz r s ? ? ? ? ? ? ? 0 100 0 0 0 ? ? ? 0 10 20 k : 5c crystal start-up time 4 low range, low power low range, high power high range, low power high range, high power 4 proper pc board layout procedures must be followed to achieve specifications. t cstl t csth ? ? ? ? 200 400 5 15 ? ? ? ? ms 6d square wave input clock frequency (erefs = 0, erclken = 1) fee or fbe mode fbelp mode f extal 0.03125 0 ? ? 40.0 50.33 mhz mhz
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 22 figure 13. typical crystal or resonator circuit: high range and low range/high gain figure 14. typical crystal or resonator circuit: low range/low gain 3.9 internal clock source (ics) characteristics table 12. ics frequency specifications (temperature range = ?40 to 85 q c ambient) num c characteristic symbol min typ 1 max unit 1p average internal reference frequency ? factory trimmed at v dd = 3.6 v and temperature = 25 q c f int_ft ? 32.768 ? khz 2p internal reference frequency ? user trimmed f int_ut 31.25 ? 39.06 khz 3t internal reference start-up time t irst ?60100 p s 4 p dco output frequency range ? trimmed 2 low range (drs=00) f dco_u 16 ? 20 mhz p mid range (drs=01) 32 ? 40 p high range (drs=10) 48 ? 60 5 p dco output frequency 2 reference = 32768 hz and dmx32 = 1 low range (drs=00) f dco_dmx32 ? 19.92 ? mhz p mid range (drs=01) ? 39.85 ? p high range (drs=10) ? 59.77 ? 6c resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) ' f dco_res_t ? r 0.1 r 0.2 %f dco 7c resolution of trimmed dco output frequency at fixed voltage and temperature (not using ftrim) ' f dco_res_t ? r 0.2 r 0.4 %f dco xosc extal xtal crystal or resonator r s c 2 r f c 1 xosc extal xtal crystal or resonator
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 23 figure 15. deviation of dco output across temperature at v dd = 3.0 v 8c total deviation of trimmed dco output frequency over voltage and temperature ' f dco_t ? + 0.5 -1.0 r 2 %f dco 9c total deviation of trimmed dco output frequency over fixed voltage and temperature range of 0 q c to 70 q c ' f dco_t ? r 0.5 r 1 %f dco 10 c fll acquisition time 3 t acquire ?? 1ms 11 c long term jitter of dco output clock (averaged over 2-ms interval) 4 c jitter ? 0.02 0.2 %f dco 1 data in typical column was characterized at 3.0 v, 25 q c or is typical recommended value. 2 the resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 this specification applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 jitter is the average deviation from the programmed freque ncy measured over the specified interval at maximum f bus . measurements are made with the device powere d by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. table 12. ics frequency specifications (temperature range = ?40 to 85 q c ambient) (continued) num c characteristic symbol min typ 1 max unit -1.00% -0.80% -0.60% -0.40% -0.20% 0.00% 0.20% 0.40% 0.60% -40 -20 0 20 40 60 80 100 120 vdd % deviation
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 24 figure 16. deviation of dco output across v dd at 25 q c 3.10 ac characteristics this section describes timing charact eristics for each peripheral system. 3.10.1 control timing table 13. control timing num c rating symbol min typ 1 max unit 1d bus frequency (t cyc = 1/f bus ) v dd t 1.8v v dd > 2.1v v dd > 2.4v f bus dc ? ? ? 10 20 25.165 mhz 2 d internal low power oscillator period t lpo 700 ? 1300 p s 3 d external reset pulse width 2 t extrst 100 ? ? ns 4 d reset low drive t rstdrv 34 x t cyc ??ns 5d bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ? ? ns 6d bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 3 t msh 100 ? ? p s -0.50% -0.40% -0.30% -0.20% -0.10% 0.00% 0.10% 0.20% 0.30% 0.40% 0.50% 2.1v 2.4v 2.7v 3.0v 3.3v 3.6v vdd % deviation
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 25 figure 17. reset timing figure 18. irq /kbipx timing 7d irq pulse width asynchronous path 2 synchronous path 4 t ilih, t ihil 100 1.5 x t cyc ? ? ? ? ns 8d keyboard interrupt pulse width asynchronous path 2 synchronous path 4 t ilih, t ihil 100 1.5 x t cyc ? ? ? ? ns 9c port rise and fall time ? low output drive (ptxds = 0) (load = 50 pf) 5 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 8 31 ? ? ns port rise and fall time ? high output drive (ptxds = 1) (load = 50 pf) slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 7 24 ? ? ns 10 voltage regulator recovery time t vrr ?4? p s 1 typical values are based on characterization data at v dd = 3.0v, 25 q c unless otherwise stated. 2 this is the shortest pulse that is guaranteed to be recogni zed as a reset or interrupt pin request. shorter pulses are not guaranteed to override reset requests from internal sources. 3 to enter bdm mode following a por, bkgd/ms should be held low during the power-up and for a hold time of t msh after v dd rises above v lvd . 4 this is the minimum pulse width that is guaranteed to pass th rough the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 5 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 q c to 85 q c. table 13. control timing (continued) num c rating symbol min typ 1 max unit t extrst reset pin t ihil kbipx t ilih irq /kbipx
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 26 3.10.2 tpm module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. figure 19. timer external clock figure 20. timer input capture pulse table 14. tpm input timing no. c function symbol min max unit 1 d external clock frequency f tclk 0f bus /4 hz 2 d external clock period t tclk 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc 5 d input capture pulse width t icpw 1.5 ? t cyc t tclk t clkh t clkl tclk t icpw tpmchn t icpw tpmchn
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 27 3.10.3 spi timing table 15 and figure 21 through figure 24 describe the timing requirements for the spi system. table 15. spi timing no. c function symbol min max unit ?d operating frequency master slave f op f bus /2048 0 f bus /2 f bus /4 hz hz 1d spsck period master slave t spsck 2 4 2048 ? t cyc t cyc 2d enable lead time master slave t lead 1 2 1 ? ? t spsck t cyc 3d enable lag time master slave t lag 1 2 1 ? ? t spsck t cyc 4d clock (spsck) high or low time master slave t wspsck t cyc ? 30 t cyc ? 30 1024 t cyc ? ns ns 5d data setup time (inputs) master slave t su 15 15 ? ? ns ns 6d data hold time (inputs) master slave t hi 0 25 ? ? ns ns 7 d slave access time t a ?1t cyc 8 d slave miso disable time t dis ?1t cyc 9d data valid (after spsck edge) master slave t v ? ? 25 25 ns ns 10 d data hold time (outputs) master slave t ho 0 0 ? ? ns ns 11 d rise time input output t ri t ro ? ? t cyc ? 25 25 ns ns 12 d fall time input output t fi t fo ? ? t cyc ? 25 25 ns ns
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 28 figure 21. spi master timing (cpha = 0) figure 22. spi master timing (cpha =1) spsck (output) spsck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (dds7 = 1, ssoe = 1). 1 2 3 4 5 6 9 10 11 12 4 9 spsck (output) spsck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in master msb out (2) master lsb out bit 6 . . . 1 port data (cpol = 0) (cpol = 1) port data ss ( 1) (output) 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: 2 1 12 11 3 4 4 11 12 5 6 9 10
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 29 figure 23. spi slave timing (cpha = 0) figure 24. spi slave timing (cpha = 1) spsck (input) spsck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12 10 spsck (input) spsck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 30 3.11 analog comparator (acmp) electricals 3.12 adc characteristics table 16. analog comparator electrical specifications c characteristic symbol min typical max unit d supply voltage v dd 1.80 ? 3.6 v c supply current (active) i ddac ?2035 p a d analog input voltage v ain v ss ? 0.3 ? v dd v c analog input offset voltage v aio 20 40 mv c analog comparator hysteresis v h 3.0 9.0 15.0 mv p analog input leakage current i alkg ??1.0 p a c analog comparator initialization delay t ainit ??1.0 p s table 17. 12-bit adc operating conditions c characteristic conditions symb min typ 1 1 typical values assume v ddad = 3.0v, temp = 25 q c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment d supply voltage absolute v ddad 1.8 ? 3.6 v delta to v dd (v dd -v ddad ) 2 2 dc potential difference. ' v ddad -100 0 +100 mv d ground voltage delta to v ss (v ss -v ssad ) 2 ' v ssad -100 0 +100 mv d ref voltage high v refh 1.8 v ddad v ddad v d ref voltage low v refl v ssad v ssad v ssad v d input voltage v adin v refl ?v refh v c input capacitance c adin ?4.55.5 pf c input resistance r adin ?5 7k : c analog source resistance 12 bit mode f adck > 4mhz f adck < 4mhz r as ? ? ? ? 2 5 k : external to mcu 10 bit mode f adck > 4mhz f adck < 4mhz ? ? ? ? 5 10 8 bit mode (all valid f adck )??10 d adc conversion clock freq. high speed (adlpc=0) f adck 0.4 ? 8.0 mhz low power (adlpc=1) 0.4 ? 4.0
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 31 figure 25. adc input impeda nce equivalency diagram table 18. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) characteristic conditions c symb min typ 1 max unit comment supply current adlpc=1 adlsmp=1 adco=1 ti ddad ? 120 ? p a supply current adlpc=1 adlsmp=0 adco=1 ti ddad ? 202 ? p a supply current adlpc=0 adlsmp=1 adco=1 ti ddad ? 288 ? p a supply current adlpc=0 adlsmp=0 adco=1 di ddad ?0.532 1 ma supply current stop, reset, module off p i ddad ? 0.007 0.8 p a adc asynchronous clock source high speed (adlpc=0) p f adack 23.35 mhz t adack = 1/f adack low power (adlpc=1) p 1.25 2 3.3 + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
mc9s08qe128 series data sheet, rev. 7 electrical characteristics freescale semiconductor 32 conversion time (including sample time) short sample (adlsmp=0) p t adc ? 20 ? adck cycles see the adc chapter in the mc9s08 qe128 reference manual for conversion time variances long sample (adlsmp=1) c ? 40 ? sample time short sample (adlsmp=0) p t ads ? 3.5 ? adck cycles long sample (adlsmp=1) c ? 23.5 ? total unadjusted error 12 bit mode t e tue ? r 3.0 ? lsb 2 includes quantization 10 bit mode p ? r 1 r 2.5 8 bit mode t ? r 0.5 1.0 differential non-linearity 12 bit mode t dnl ? r 1.75 ? lsb 2 10 bit mode 3 p? r 0.5 r 1.0 8 bit mode 3 t? r 0.3 r 0.5 integral non-linearity 12 bit mode t inl ? r 1.5 ? lsb 2 10 bit mode t ? r 0.5 r 1.0 8 bit mode t ? r 0.3 r 0.5 zero-scale error 12 bit mode t e zs ? r 1.5 ? lsb 2 v adin = v ssad 10 bit mode p ? r 0.5 r 1.5 8 bit mode t ? r 0.5 r 0.5 full-scale error 12 bit mode t e fs ? r 1.0 ? lsb 2 v adin = v ddad 10 bit mode p ? r 0.5 r 1 8 bit mode t ? r 0.5 r 0.5 quantization error 12 bit mode d e q ?-1 to 0? lsb 2 10 bit mode ? ? r 0.5 8 bit mode ? ? r 0.5 input leakage error 12 bit mode d e il ? r 2?lsb 2 pad leakage 4 * r as 10 bit mode ? r 0.2 r 4 8 bit mode ? r 0.1 r 1.2 temp sensor slope -40 q c to 25 q c d m ? 1.646 ? mv/ q c 25 q c to 85 q c ? 1.769 ? temp sensor voltage 25 q cdv temp25 ?701.2? mv 1 typical values assume v ddad = 3.0v, temp = 25 q c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 1 lsb = (v refh - v refl )/2 n 3 monotonicity and no-missing-codes guaranteed in 10 bit and 8 bit modes 4 based on input pad leakage current. refer to pad electricals. table 18. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) (continued) characteristic conditions c symb min typ 1 max unit comment
electrical characteristics mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 33 3.13 flash specifications this section provides details about program/erase ti mes and program-erase endurance for the flash memory. program and erase operations do not require any special power sources ot her than the normal v dd supply. for more detailed information about program/erase operat ions, see the memory section of the mc9s08qe128 reference manual . table 19. flash characteristics c characteristic symbol min typical max unit d supply voltage for program/erase -40 q c to 85 q cv prog/erase 1.8 3.6 v d supply voltage for read operation v read 1.8 3.6 v d internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz d internal fclk period (1/fclk) t fcyc 56.67 p s p byte program time (random location) (2) t prog 9t fcyc p byte program time (burst mode) (2) t burst 4t fcyc p page erase time 2 2 these values are hardware state machi ne controlled. user code doe s not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc p mass erase time (2) t mass 20,000 t fcyc byte program current 3 3 the program and erase currents are additional to the standard run i dd . these values are measur ed at room temperatures with v dd = 3.0 v, bus frequency = 4.0 mhz. r iddbp ?4?ma page erase current 3 r iddpe ?6?ma c program/erase endurance 4 t l to t h = ?40 q c to + 85 q c t = 25 q c 4 typical endurance for flash was evaluated for this product family on th e hc9s12dx64. for additional information on how freescale defines typical endurance, plea se refer to engineering bulletin eb619, typical endurance for nonvolatile memory . 10,000 ? ? 100,000 ? ? cycles c data retention 5 5 typical data retention values are based on intrinsic capability of th e technology measured at high temperature and de-rated to 25 q c using the arrhenius equation. for additional informat ion on how freescale defines typical data retention, please refer to engineering bulletin eb618, typical data retention for nonvolatile memory. t d_ret 15 100 ? years
mc9s08qe128 series data sheet, rev. 7 ordering information freescale semiconductor 34 4 ordering information this section contains ordering information for mc9s08qe128, mc9s08qe96, and mc9s08qe64 devices. 4.1 device numbering system example of the device numbering system: 5 package information the below table details the various packages available. table 20. ordering information freescale part number 1 1 see the reference manual, mc9s08qe128rm , for a complete description of modules included on each device. memory temperature range ( q c) package 2 2 see table 21 for package information. flash ram mc9s08qe128clk 128k 8k -40 to +85 80 lqfp mc9s08qe128clh -40 to +85 64 lqfp mc9s08qe128cft -40 to +85 48 qfn mc9s08qe128cld -40 to +85 44 lqfp mc9s08qe96clk 96k 6k -40 to +85 80 lqfp mc9s08qe96clh -40 to +85 64 lqfp MC9S08QE96CFT -40 to +85 48 qfn mc9s08qe96cld -40 to +85 44 qfp mc9s08qe64clh 64k 4k -40 to +85 64 lqfp mc9s08qe64cft -40 to +85 48 qfn mc9s08qe64cld -40 to +85 44 qfp mc9s08qe64clc -40 to +85 32 lqfp table 21. package descriptions pin count package type abbreviation designator case no. document no. 80 low quad flat package lqfp lk 917a 98ass23237w 64 low quad flat package lqfp lh 840f 98ass23234w 48 quad flat no-leads qfn ft 1314 98arh99048a 44 low quad flat package lqfp ld 824d 98ass23225w 32 low quad flat package lqfp lc 873a 98ash70029a mc temperature range family memory status core (c = ?40 q c to 85 q c) (9 = flash-based) 9 s08 xx (mc = fully qualified) package designator (see table 21 ) approximate flash size in kbytes qe 128 c
package information mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 35 5.1 mechanical drawings the following pages are mechanical draw ings for the packages described in table 21 . for the latest available drawings please visit our web site ( http://www.freescale.com ) and enter the package?s document nu mber into the keyword search box.
mc9s08qe128 series data sheet, rev. 7 package information freescale semiconductor 36 figure 26. 80-pin lqfp package dr awing (case 917a, doc #98ass23237w) 1 20 21 40 41 60 61 80 view aa ??? ??? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?l?, ?m? and ?n? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?t?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.460 (0.018). minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). ab view y (k) (z) (w) view aa dim a min max min max inches 14.00 bsc 0.551 bsc millimeters a1 7.00 bsc 0.276 bsc b 14.00 bsc 0.551 bsc b1 7.00 bsc 0.276 bsc c ??? 1.60 ??? 0.063 c1 0.04 0.24 0.002 0.009 c2 1.30 1.50 0.051 0.059 d 0.22 0.38 0.009 0.015 e 0.40 0.75 0.016 0.030 f 0.17 0.33 0.007 0.013 g 0.65 bsc 0.026 bsc j 0.09 0.27 0.004 0.011 k 0.50 ref 0.020 ref p 0.325 bsc 0.013 ref r1 0.10 0.20 0.004 0.008 s 16.00 bsc 0.630 bsc s1 8.00 bsc 0.315 bsc u 0.09 0.16 0.004 0.006 v 16.00 bsc 0.630 bsc v1 8.00 bsc 0.315 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref 0 01 ??? ??? 02 c2 c1 c l 0 10 0 9 14 0 10 0 9 14 l?m 0.20 (0.008) h n 4x 3x view y ?l? l?m 0.20 (0.008) t n ?m? b v v1 b1 ?n? s1 a1 s a 4x 20 tips seating 0.10 (0.004) t ?h? plane ?t? 8x c 2 gage 0.25 (0.010) plane 2x r r1 e 1 s 0.05 (0.002) ab ?x? x= l, m, n p g plating base metal j u f d section ab?ab s l?m m 0.13 (0.005) n s t rotated 90 clockwise case 917a-02 issue c date 09/21/95
package information mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 37 figure 27. 64-pin lqfp package drawing (case 840f, doc #98ass23234w), sheet 1 of 3
mc9s08qe128 series data sheet, rev. 7 package information freescale semiconductor 38 figure 28. 64-pin lqfp package drawing (case 840f, doc #98ass23234w), sheet 2 of 3
package information mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 39 figure 29. 64-pin lqfp package drawing (case 840f, doc #98ass23234w), sheet 3 of 3
mc9s08qe128 series data sheet, rev. 7 package information freescale semiconductor 40 figure 30. 48-pin qfn package drawing (case 1314, doc #98arh99048a), sheet 1 of 3
package information mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 41 figure 31. 48-pin qfn package drawing (case 1314, doc #98arh99048a), sheet 2 of 3
mc9s08qe128 series data sheet, rev. 7 package information freescale semiconductor 42 figure 32. 48-pin qfn package drawing (case 1314, doc #98arh99048a), sheet 3 of 3
package information mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 43 figure 33. 44-pin lqfp package drawing (c ase 824d, doc #98ass23225w), sheet 1 of 3
mc9s08qe128 series data sheet, rev. 7 package information freescale semiconductor 44 figure 34. 44-pin lqfp package drawing (c ase 824d, doc #98ass23225w), sheet 2 of 3
package information mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 45 figure 35. 44-pin lqfp package drawing (c ase 824d, doc #98ass23225w), sheet 3 of 3
mc9s08qe128 series data sheet, rev. 7 package information freescale semiconductor 46 figure 36. 32-pin lqfp package drawing (cas e 873a, doc #98ash70029a), sheet 1 of 3
package information mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 47 figure 37. 32-pin lqfp package drawing (cas e 873a, doc #98ash70029a), sheet 2 of 3
mc9s08qe128 series data sheet, rev. 7 package information freescale semiconductor 48 figure 38. 32-pin lqfp package drawing (cas e 873a, doc #98ash70029a), sheet 3 of 3
product documentation mc9s08qe128 series data sheet, rev. 7 freescale semiconductor 49 6 product documentation find the most current versions of all documents at: http://www.freescale.com 7 revision history to provide the most up-to-date information, the revision of our documents on the world wide we b are the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.freescale.com the following revision history table summarizes changes contained in this document. reference manual (mc9s08qe128rm) contains extensive product information including modes of operation, memory, resets and interrupts, register defin ition, port pins, cpu, and all module information. table 22. revision history revision date description of changes 4 9 nov 2007 replaced 44 qfp package with 44 lqfp package. changed acmp electricals, v aio specification?s test category from p to c. 5 28 may 2008 updated the tables thermal characteristics , dc characteristics , supply current characteristics , xosc and ics specifications (temperature range = ?40 to 85c ambient) , ics frequency specifications (temperature range = ?40 to 85c ambient) , control timing , and analog comparator electrical specifications , 12-bit adc characteristics (vrefh = vddad, vrefl = vssad) updated the figures typical run idd for fbe and fei, idd vs. vdd (acmp and adc off, all other modules enabled) , deviation of dco output fr om trimmed frequency (50.33 mhz, 3.0 v) , and deviation of dco output from tr immed frequency (50.33 mhz, 25c) 6 24 jun 2008 updated the table thermal characteristics updated the row corresponding to num 18 in the table dc characteristics updated the tables mc9s08 qe128 series features by mcu and package , dc characteristics , supply current characteristics , thermal characteristics , control timing , and ordering information updated the figures typical run idd for fbe and fei, idd vs. vdd (adc off, all other modules enabled) , deviation of dco output across temperature at vdd = 3.0 v , and deviation of dco output across vdd at 25c 7 2 oct 2008 updated the stop2 and stop3 mode supply current in the supply current characteristics table. replaced the stop mode adders section from the supply current characteristics with its own stop mode adders table with new specifications.
document number: mc9s08qe128 rev. 7 10/2008 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunde r to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental dam ages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable atto rney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are t he property of their respective owners. ? freescale semiconductor, inc. 2008. all rights reserved.

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